As an introduction to the problems solved by the present invention, consider a composite signal 10 containing both amplitude modulated information during a first period 12 and a synchronization signal, sometimes called a "sync" signal during a second period 13 as shown generally in FIG. 1. Such signals are useful in instrumentation telemetry and communications systems, to name a few technologies, where a processor of analog information must be synchronized with the source of analog signals.
At the processor, sync signal 16 is separated from composite signal 10 to facilitate clock recovery. Conventional clock recovery circuits include a phase locked loop having a binary counter as a delay element. The carry signal, provided when the maximum count (N) of the counter is exceeded, is connected to a phase comparator of the loop along with the sync signal. The error signal resulting from phase comparison and low-pass filtering will keep a variable frequency oscillator (VFO) of the loop locked at a frequency N times the sync frequency. The clock recovered by the phase locked loop is then used to control sampling of the amplitude modulated portion of composite signal 10.
Serial to parallel conversion of a number of samples is conventionally accomplished by separately addressing a memory device for each sample so that a number of samples can be provided in parallel. Where an analog memory, such as a charge storage device, is used, a shifting scheme is conventionally employed to simplify addressing. Where digital conversion and storage is used, a barrel shifter, or random access memory is conventionally employed with more complex addressing circuitry.
The serial to parallel circuit architecture described above is costly to implement as an integrated circuit. That architecture requires considerable surface area on the integrated circuit substrate, is adversely complex so that reliability and manufacturing yields cannot be further improved, suffers from considerable power consumption, and generates an adverse amount of heat.
In view of the problems described above and related problems that consequently become apparent to those skilled in the applicable arts, the need remains in serial to parallel conversion circuits and in systems for sampling composite signals for a serial to parallel conversion circuit especially for use on an integrated circuit substrate.